1. Field of Invention
Embodiments of the present invention relate generally to communications systems such as routers. More particularly, the embodiments of the present invention relate to the determination of the size of the stashing in semiconductor memory devices.
2. Description of the Background Art
As the demands of the networking and telecommunication markets are growing, communication protocols are becoming increasing complex. This, in turn, demands higher performance of the communication systems.
The performance-enhancing features of communication systems include stashing the received information. When a networking device such as an Ethernet controller receives an information packet, information is copied to the layer-2 cache, along with the writing, into the main memory (e.g., Double Data Rate memory). This is referred to as ‘stashing’. Stashing ensures that when the network device interrupts the CPU, and the CPU running the network device driver's interrupt handler needs to process the packet, the information packet is already present in the layer-2 cache. Therefore, the CPU does not need to go to the main memory to fetch the packet. This, in turn, improves the router's performance.
Conventional techniques for stashing involve configuring the stashing size manually. Further, the programmer needs to configure the index (offset) of the information packet for the stashing. Manual/static stashing may not be able to adjust the stashing size, based on the information of the packet, thereby utilizing the performance of the processor optimally.